Datasheet4U.com

74LV00A Datasheet PDF

Nexperia 74LV00A

The 74LV00A is a quad 2-input NAND gate. This feature allows the use of these devices as translators in mixed voltage environments. This device is fully specified for partial power down applications using IOFF.
Part No. 74LV00A
Datasheet 74LV00A Download
Manufacturer
Nexperia
Description Quad 2-input NAND gate
Buy Stock & Price
74LV00A datasheet page 1 preview

FEATURES AND BENEFITS

● Wide supply voltage range from 2.0 V to 5.5 V
● Maximum tpd of 9 ns at 5 V
● Typical VOL(p) < 0.8 V at VCC = 3.3 V, Tamb = 25 °C
● Typical VOH(v) > 2.3 V at VCC = 3.3 V, Tamb = 25 °C
● Supports mixed-mode voltage operation on all ports
● IOFF circuitry provides partial Power-down mode operation
● Latch-up performance exceeds 250 mA per JESD 78 Class II
● ESD protection:
● MM: MM JESD22-A115-B exceeds 200 V
● HBM: ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 4 kV
● CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 2 kV
● Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74LV00APW -40 °C to +125 °C Name TSSOP14

DESCRIPTION

plastic thin shrink small outline package; 14 leads; body width 4.4 mm Version SOT402-1 Nexperia 4. Functional diagram 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 1Y 3 2Y 6 3Y 8 4Y 11 mna212 Fig. 1. Logic symbol 1 2& 3 4 5& 6 9 10 & 8 12 13 & 11 mna246 Fig. 2.
74LV00A page 2 preview 74LV00A page 3 preview