74LV14D
Overview
The 74LV14 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC14 and 74HCT14. The 74LV14 provides six inverting buffers with Schmitt-trigger input.
- Wide supply voltage range from 1.0 V to 5.5 V
- CMOS low power dissipation
- Optimized for low voltage applications: 1.0 V to 3.6 V
- Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
- Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
- Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
- Complies with JEDEC standards:
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
