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74LV165D - 8-bit parallel-in/serial-out shift register

This page provides the datasheet information for the 74LV165D, a member of the 74LV165 8-bit parallel-in/serial-out shift register family.

Datasheet Summary

Description

The 74LV165 is an 8-bit serial or parallel-in/serial-out shift register.

Features

  • Wide supply voltage range from 1.0 to 5.5 V.
  • CMOS low power dissipation.
  • Direct interface with TTL levels (2.7 V to 3.6 V).
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Optimized for low voltage.

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Datasheet preview – 74LV165D

Datasheet Details

Part number 74LV165D
Manufacturer nexperia
File Size 274.14 KB
Description 8-bit parallel-in/serial-out shift register
Datasheet download datasheet 74LV165D Datasheet
Additional preview pages of the 74LV165D datasheet.

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Full PDF Text Transcription

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74LV165 8-bit parallel-in/serial-out shift register Rev. 9 — 5 September 2022 Product data sheet 1. General description The 74LV165 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. When PL is HIGH data enters the register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH on CE will disable the CP input. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. 2.
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