74LV74-Q100 Datasheet | Nexperia

description The 74LV74-Q100 is a dual positive edge triggered D-type flip-flop with individual data (n D), clock (n CP), set (n SD) and reset (n RD) inputs, and plementary n Q and n Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the n Q output. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits - Automotive product qualification in accordance with AEC-Q100 (Grade 1) - Specified from -40 °C to +85 °C and from -40 °C to +125 °C - Wide supply voltage range from 1.0 V to 5.5 V - Optimized for low voltage applications from 1.0 V to 3.6 V - CMOS low power dissipation - Latch-up performance exceeds 100 m A per JESD 78 Class II Level B - Direct interface with TTL levels (2.7 V to 3.6 V) - ESD protection: - MIL-STD-833, method 3015 exceeds 2000 V - HBM JESD22-A114F exceeds 2000 V - MM JESD22-A115-A exceeds 200 V (C = 200 p F, R = 0 Ω) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74LV74D-Q100 -40 °C to +125 °C SO14 74LV74PW-Q100 -40 °C to +125 °C TSSOP14 Description Version plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 plastic thin shrink small outline package; 14 leads; SOT402-1 body width 4.4 mm Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 4. Functional diagram 4 10 1SD 2SD 2 12 1D 2D 1Q 2Q 5 9 3 1CP CP 11...