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74LVC126AD - Quad buffer/line driver

Download the 74LVC126AD datasheet PDF. This datasheet also covers the 74LVC126A variant, as both devices belong to the same quad buffer/line driver family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74LVC126A is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE).

A LOW on nOE causes the outputs to assume a high impedance OFF-state.

Inputs can be driven from either 3.3 V or 5 V devices.

Key Features

  • Overvoltage tolerant inputs to 5.5 V.
  • Wide supply voltage range from 1.2 V to 3.6 V.
  • CMOS low power consumption.
  • Direct interface with TTL levels.
  • Complies with JEDEC standard:.
  • JESD8-7A (1.65 V to 1.95 V).
  • JESD8-5A (2.3 V to 2.7 V).
  • JESD8-C/JESD36 (2.7 V to 3.6 V).
  • ESD protection:.
  • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V.
  • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V.
  • Sp.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74LVC126A-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by Nexperia

Part Number Description
74LVC126A Quad buffer/line driver
74LVC126A-Q100 Quad buffer/line driver
74LVC125A Quad buffer/line driver
74LVC125A-Q100 Quad buffer/line driver
74LVC10A Triple 3-input NAND gate

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74LVC126A Quad buffer/line driver with 5 V tolerant input/outputs; 3-state Rev. 14 — 2 May 2025 Product data sheet 1. General description The 74LVC126A is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2.