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74LVC1G80 - Single D-type flip-flop

General Description

The 74LVC1G80 is a single positive-edge triggered D-type flip-flop.

Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output.

Key Features

  • Wide supply voltage range from 1.65 V to 5.5 V.
  • Overvoltage tolerant inputs to 5.5 V.
  • High noise immunity.
  • ±24 mA output drive (VCC = 3.0 V).
  • CMOS low power dissipation.
  • Direct interface with TTL levels.
  • IOFF circuitry provides partial Power-down mode operation.
  • Latch-up performance exceeds 250 mA.
  • Complies with JEDEC standard:.
  • JESD8-7 (1.65 V to 1.95 V).
  • JESD8-5 (2.3 V to 2.7 V).
  • JESD8C.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74LVC1G80 Single D-type flip-flop; positive-edge trigger Rev. 15 — 29 March 2022 Product data sheet 1. General description The 74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF.