Description
The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.
The set and reset are asynchronous active LOW inputs and operate independently of the clock input.
Features
- 5 V tolerant inputs for interlacing with 5 V logic.
- Wide supply voltage range from 1.2 V to 3.6 V.
- CMOS low power consumption.
- Direct interface with TTL levels.
- Complies with JEDEC standard:.
- JESD8-7A (1.65 V to 1.95 V).
- JESD8-5A (2.3 V to 2.7 V).
- JESD8-C/JESD36 (2.7 V to 3.6 V).
- ESD protection:.
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V.
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000.
74LVC74AD Datasheet
