Datasheet4U Logo Datasheet4U.com

HEF4040B-Q100 - 12-stage binary ripple counter

Description

The HEF4040B-Q100 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11).

The counter advances on the HIGH-to-LOW transition of CP.

Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 3).
  • Specified from 40 C to +85 C.
  • Tolerant of slow clock rise and fall time.
  • Fully static operation.
  • 5 V, 10 V, and 15 V parametric ratings.
  • Standardized symmetrical output characteristics.
  • ESD protection:.
  • MIL-STD-883, method 3015 exceeds 2000 V.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ).
  • Complies with JEDEC standard JESD 13-B.

📥 Download Datasheet

Datasheet preview – HEF4040B-Q100

Datasheet Details

Part number HEF4040B-Q100
Manufacturer nexperia
File Size 674.54 KB
Description 12-stage binary ripple counter
Datasheet download datasheet HEF4040B-Q100 Datasheet
Additional preview pages of the HEF4040B-Q100 datasheet.

📁 Similar Datasheet

  • HEF4040B - 12-stage binary counter (NXP)
  • HEF4041B - Quadruple true/complement buffer (NXP)
  • HEF4042B - Quadruple D-latch (NXP)
  • HEF4043B - Quadruple R/S latch with 3-state outputs (NXP)
  • HEF4043B - Quadruple R/S latch (Philips)
  • HEF4044B - Quadruple R/S latch (NXP)
  • HEF4046B - Phase-locked loop (NXP)
  • HEF4046B - Phase-locked loop (Philips)
  • HEF4047B - Monostable/astable multivibrator (NXP)
  • HEF4047B - Monostable/astable multivibrator (Philips)
Other Datasheets by nexperia

Full PDF Text Transcription

Click to expand full text
HEF4040B-Q100 12-stage binary ripple counter Rev. 1 — 4 April 2013 Product data sheet 1. General description The HEF4040B-Q100 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop. The clock input is highly tolerant of slow rise and fall times due to its Schmitt trigger action. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.
Published: |