NPIC6C596A-Q100 Datasheet PDF (Power logic 8-bit shift register)

NPIC6C596A-Q100 - Power logic 8-bit shift register

Datasheet Summary

Description

The NPIC6C596A-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and open-drain outputs.

Both the shift and storage register have separate clocks.

Features

Automotive product qualification in accordance with AEC-Q100 (Grade 1).
Specified from -40 °C to +85 °C and from -40 °C to +125 °C.
Wide supply range 2.3 V to 5.5 V.
Low RDSon.
Eight Power EDNMOS transistor outputs of 100 mA continuous current.
250 mA current limit capability.
Output clamping voltage 33 V.
30 mJ avalanche energy capability.
Enhanced cascading for multiple stages.
All registers cleared with.

Datasheet Details

Part number	NPIC6C596A-Q100
Manufacturer	nexperia
File Size	280.64 KB
Description	Power logic 8-bit shift register
Datasheet	NPIC6C596A-Q100 Datasheet
Additional preview pages of the NPIC6C596A-Q100 datasheet.

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Full PDF Text Transcription

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NPIC6C596A-Q100 Power logic 8-bit shift register; open-drain outputs Rev. 2 — 26 June 2020 Product data sheet 1. General description The NPIC6C596A-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and open-drain outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR resets both the shift register and storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input.

Published: Jul 5, 2019 |