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FDC6321C Datasheet PDF

onsemi FDC6321C

This very high density process is especially tailored to minimize on−state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors in load switching applications.
Part No. FDC6321C
Datasheet FDC6321C Download
Manufacturer
onsemi
Description Dual N & P-Channel Digital FET
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FDC6321C datasheet page 1 preview

GENERAL DESCRIPTION

These dual N & P Channel logic level enhancement mode field effect transistors are produced using onsemi’s proprietary, high cell density, DMOS technology. Since bias resistors are not required this dual digital FET can replace several digital transistors with different bias resistors.

FEATURES

● N−Channel 0.68 A, 25 V RDS(ON) = 0.45 W @ VGS = 4.5 V
● P−Channel −0.46 A, −25 V RDS(ON) = 1.1 W @ VGS = −4.5 V
● Very Low Level Gate Drive Requirements Allowing Direct Operation in 3 V Circuits. VGS(th) < 1.0 V.
● Gate−Source Zener for ESD Ruggedness. >6 kV Human Body Model
● Replace Multiple Dual NPN & PNP Digital Transistors
● This is a Pb−Free Device DATA SHEET VDSS 25 V VDSS −25 V N−Channel RDS(ON) MAX 0.45 W @ 4.5 V ID MAX 0.68 A P−Channel RDS(ON) MAX 1.1 W @ −4.5 V ID MAX −0.46 A D2 S1 D1 G2 G1S2 TSOT23 6−Lead SUPERSOTt−6 CASE 419BL MARKING DIAGRAM 321 MG G 1 321 = Specific Device Code M = Assembly Operation Month G = Pb−Free Package (Note: Microdot may be in either...
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