onsemi MC10E150
The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent and input data transitions propagate through to the output. The Master Reset (MR) overrides all other controls to set the Q outputs low.| Part No. | MC10E150 |
|---|---|
| Datasheet | MC10E150 Download |
| Manufacturer |  onsemi |
| Description | 6-BIT D LATCH |
| Buy | Stock & Price |
DESCRIPTION
A logic HIGH on either LEN1 or LEN2 (or both) latches the data. The 100 Series contains temperature compensation.FEATURES
● 800 ps Max. Propagation Delay● PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
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● with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input 50 kW Pulldown Resistors ESD Protection: Human Body Model; > 2 kV, Machine Model; > 200 V Charged Device Model; > 2 kV Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test Moisture Sensitivity Level: Pb = 1 Pb−Free = 3 For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 173 devices Pb−Free Packages are Available* PLCC−28 FN SUFFIX CASE 776 MARKING DIAGRAM* 1 MCxxxE150FNG AWLYYWW
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● xxx A WL YY WW G = 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION...
