TM57PA40 Description
............................................................................................. CPU Core ..................................................................................................................... 5 1.1 Clock Scheme and Instruction Cycle.......................................................................
TM57PA40 Key Features
- 5 1.1 Clock Scheme and Instruction Cycle
- 5 1.2 Addressing Mode
- 5 1.3 Programming Counter (PC) and Stack
- 6 1.4 ALU and Working (W) Register
- 6 1.5 STATUS Register
- 6 1.6 Interrupt
- 8 2.1 Reset
- 8 2.2 System Configuration Register (SYSCFG)
- 8 2.3 PROM Re-use
- 9 2.4 Power-Down Mode