| Part Number | 74HC112 Datasheet |
|---|---|
| Manufacturer | Texas Instruments |
| Overview |
The ’HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the ot.
* Wide operating voltage range of 2 V to 6 V * Outputs can drive up to 10 LSTTL loads * Low power consumption, 40-μA max ICC * Typical tpd = 13 ns * ±4-mA output drive at 5 V * Low input current of 1 μA max 2 Description The ’HC112 devices contain two independent J-K negative-edge-triggered flip-f. |
74HC112 Datasheet and Specifications PDF
The 74HC112 is a Dual J-K Negative-Edge-Triggered Flip-Flops.
Key Specifications
| Package | TSSOP |
|---|---|
| Mount Type | Surface Mount |
| Pins | 16 |
| Operating Voltage | 4.5 V |
| Max Voltage (typical range) | 6 V |
| Min Voltage (typical range) | 2 V |
| Logic Function | AND, Flip-Flop, JK-Type |
| Clock Edge Trigger | Negative Edge |
| Part Number | 74HC112 Datasheet |
|---|---|
| Description | Dual JK flip-flop |
| Manufacturer | Philips Semiconductors |
| Overview |
The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT112 are dual ne.
* Asynchronous set and reset * Output capability: standard * ICC category: flip-flops GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT112 are d. |
| Part Number | 74HC112 Datasheet |
|---|---|
| Description | Dual JK flip-flop |
| Manufacturer | Nexperia |
| Overview | The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. . individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the . |