| Part Number | 74LS174 |
|---|---|
| Manufacturer | Hitachi Semiconductor |
| Overview | 19.20 20.00 Max 16 9 7.40 Max 6.30 Unit: mm 1 1.3 1.11 Max 8 0.51 Min 2.54 Min 5.06 Max 7.62 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) + 0. s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the informat. |
74LS174 Datasheet
The 74LS174 is a Hex/Quadruple D-type Flip-Flips.
| Part Number | 74LS174 |
|---|---|
| Description | Hex/Quad D Flip-Flops |
| Manufacturer | National Semiconductor |
| Overview | These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic All have a direct clear input and the quad (175) versions feature complementary outputs from each fli. Y Y Y Y Y Y Y Y LS174 contains six flip-flops with single-rail outputs LS175 contains four flip-flops with double-rail outputs Buffered clock and direct clear inputs Individual data input to each flip-flop Applications include Buffer storage registers Shift registers Pattern generators Typical clo. |
| Part Number | 74LS174 |
|---|---|
| Description | LOW POWER SCHOTTKY |
| Manufacturer | onsemi |
| Overview |
The LS174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input’s state is transferred to.
4D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel
© Semiconductor Components Industries, LLC, 1999
1
December, 1999 * Rev. 6 Publication Order Number: SN74LS174/D SN74LS174 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Q5 15 D5 14 D4 13 Q4 12 D3 11 Q3 10 CP 9 NOTE: The Flatpak ve. |
| Part Number | 74LS174 |
|---|---|
| Description | HEX D FLIP-FLOP |
| Manufacturer | Motorola Semiconductor |
| Overview |
The LS174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input’s state is transferred to .
6
HIGH D0 * D5 CP MR Q0 * Q5 Data Inputs Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Outputs (Note b) 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Cer. |