74LVC2G38 Datasheet and Specifications PDF

The 74LVC2G38 is a Dual 2-input NAND gate.

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Part Number74LVC2G38 Datasheet
ManufacturerNXP Semiconductors
Overview The 74LVC2G38 provides a 2-input NAND function. The outputs of the 74LVC2G38 devices are open-drain and can be connected to other open-drain outputs to implement active-LOW, wired-OR or active-HIGH wi. and benefits
* Wide supply voltage range from 1.65 V to 5.5 V
* 5 V tolerant outputs for interfacing with 5 V logic
* High noise immunity
* Complies with JEDEC standard:
* JESD8-7 (1.65 V to 1.95 V)
* JESD8-5 (2.3 V to 2.7 V)
* JESD8B/JESD36 (2.7 V to 3.6 V)
* ESD protection:
* HBM EIA/JESD22-A114F .
Part Number74LVC2G38 Datasheet
DescriptionDUAL 2-INPUT NAND GATE
ManufacturerDiodes Incorporated
Overview Pin Assignments The 74LVC2G38 is a dual, two input NAND gate with open-drain outputs. Both gates have open-drain outputs designed for operation over a power supply range of 1.65V to 5.5V. The device.
* Wide Supply Voltage Range from 1.65V to 5.5V
* Outputs Sink 24mA at Vcc = 3.3V
* CMOS Low Power Consumption
* IOFF Supports Partial-Power-Down Mode Operation
* Inputs accept up to 5.5V
* Schmitt Trigger Action at all inputs makes the circuit tolera.
Part Number74LVC2G38 Datasheet
DescriptionDual 2-input NAND gate
ManufacturerNexperia
Overview The 74LVC2G38 is a dual 2-input NAND gate with open-drain outputs. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and. and benefits
* Wide supply voltage range from 1.65 V to 5.5 V
* 5 V tolerant outputs for interfacing with 5 V logic
* Overvoltage tolerant inputs to 5.5 V
* High noise immunity
* CMOS low power dissipation
* IOFF circuitry provides partial Power-down mode operation
* Complies with JEDEC standard:
* .