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74LVC2G38 - Dual 2-input NAND gate

Datasheet Summary

Description

The 74LVC2G38 is a dual 2-input NAND gate with open-drain outputs.

Inputs can be driven from either 3.3 V or 5 V devices.

This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Features

  • Wide supply voltage range from 1.65 V to 5.5 V.
  • 5 V tolerant outputs for interfacing with 5 V logic.
  • Overvoltage tolerant inputs to 5.5 V.
  • High noise immunity.
  • CMOS low power dissipation.
  • IOFF circuitry provides partial Power-down mode operation.
  • Complies with JEDEC standard:.
  • JESD8-7 (1.65 V to 1.95 V).
  • JESD8-5 (2.3 V to 2.7 V).
  • JESD8C (2.7 V to 3.6 V).
  • JESD36 (4.5 V to 5.5 V).

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Datasheet Details

Part number 74LVC2G38
Manufacturer nexperia
File Size 298.24 KB
Description Dual 2-input NAND gate
Datasheet download datasheet 74LVC2G38 Datasheet
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74LVC2G38 Dual 2-input NAND gate; open drain Rev. 14 — 21 June 2022 Product data sheet 1. General description The 74LVC2G38 is a dual 2-input NAND gate with open-drain outputs. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • Wide supply voltage range from 1.65 V to 5.
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