| Overview |
The 82S09 is a 576-Bit, Schottky clamped TTL, random access memory, organized as 64X9. This organization allows byte manipulation of data, including parity. Where parity is not monitored, the ninth bi.
open collector outputs, chip enable input, and a very low current PNP input structure to enhance memory expansion.
During WRITE operation, the logic state of the device output follows the complement of the data input being written. This feature allows faster execution of WR ITEREAD cycles, enhancing.
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