| Part Number | 9DBL0641 Datasheet |
|---|---|
| Manufacturer | Renesas |
| Overview | The 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 buffers are low-power, high-performance members of Renesas' full featured PCIe family. The buffers support PCIe Gen1 through Gen5. PCIe Clocking Architectures . ▪ 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair ▪ 9DBLxx4x devices provide integrated 100Ω terminations ▪ 9DBLxx5x devices provide integrated 85Ω terminations ▪ See AN-891 for easy coupling to other logic families ▪ Spread-spectrum compatible ▪ Dedicated OE# pin for e. |
9DBL0641 Datasheet and Specifications PDF
The 9DBL0641 is a Zero-Delay/Fanout Buffer.
Key Specifications
| Mount Type | Surface Mount |
|---|---|
| Pins | 40 |
| Operating Voltage | 3.3 V |
| Max Voltage (typical range) | 3.465 V |
| Min Voltage (typical range) | 3.135 V |
| Output Type (varies by manufacturer) | LP-HCSL |
| Height | 900 µm |
| Length | 5 mm |
| Part Number | 9DBL0641 Datasheet |
|---|---|
| Description | 6-output 3.3V PCIe Zero-Delay Buffer |
| Manufacturer | IDT |
| Overview |
The 9DBL0641 / 9DBL0651 devices are 3.3V members of IDT's Full-Featured PCIe family. The 9DBL06 supports PCIe Gen1-4 Common Clocked (CC) and PCIe Separate Reference Independent Spread (SRIS) systems. .
* 6 * 1-200 MHz Low-Power (LP) HCSL DIF pairs * 9DBL0641 default ZOUT = 100 * 9DBL0651 default ZOUT = 85 * 9DBL06P1 factory programmable defaults Key Specifications * PCIe Gen1-2-3-4 CC compliant in ZDB mode * PCIe Gen2 SRIS compliant in ZDB mode * Supports PCIe Gen2-3 SRIS in fan-out mode * DIF c. |