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9DBL0641 - 6-output 3.3V PCIe Zero-Delay Buffer

Datasheet Summary

Description

The 9DBL0641 / 9DBL0651 devices are 3.3V members of IDT's Full-Featured PCIe family.

The 9DBL06 supports PCIe Gen1-4 Common Clocked (CC) and PCIe Separate Reference Independent Spread (SRIS) systems.

Features

  • 6.
  • 1-200 MHz Low-Power (LP) HCSL DIF pairs.
  • 9DBL0641 default ZOUT = 100.
  • 9DBL0651 default ZOUT = 85.
  • 9DBL06P1 factory programmable defaults Key Specifications.
  • PCIe Gen1-2-3-4 CC compliant in ZDB mode.
  • PCIe Gen2 SRIS compliant in ZDB mode.
  • Supports PCIe Gen2-3 SRIS in fan-out mode.
  • DIF cycle-to-cycle jitter.

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Datasheet preview – 9DBL0641

Datasheet Details

Part number 9DBL0641
Manufacturer IDT
File Size 300.43 KB
Description 6-output 3.3V PCIe Zero-Delay Buffer
Datasheet download datasheet 9DBL0641 Datasheet
Additional preview pages of the 9DBL0641 datasheet.

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Full PDF Text Transcription

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6-output 3.3V PCIe Zero-Delay Buffer 9DBL0641 / 9DBL0651 DATASHEET Description The 9DBL0641 / 9DBL0651 devices are 3.3V members of IDT's Full-Featured PCIe family. The 9DBL06 supports PCIe Gen1-4 Common Clocked (CC) and PCIe Separate Reference Independent Spread (SRIS) systems. It offers a choice of integrated output terminations providing direct connection to 85Ω or 100Ω transmission lines. The 9DBL06P1 can be factory programmed with a user-defined power up default SMBus configuration.
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