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9DBL0643 - 6-output 3.3V LP-HCSL Zero-Delay Buffer

General Description

The 9DBL06x3 devices are 3.3V members of IDT's Full-Featured PCIe clock family.

They support PCIe Gen1-4 Common Clock (CC) architectures and also support NVLINK applications.

The 9DBL06x3 parts have a Loss of Signal (LOS) indicator to support fault-tolerant, high reliability systems.

Key Features

  • Loss Of Signal (LOS) open drain output.
  • 6.
  • 1-200 MHz Low-Power (LP) HCSL DIF pairs.
  • 9DBL0643 default Zout = 100Ω.
  • 9DBL0653 default Zout = 85Ω.
  • Easy AC-coupling to other logic families, see IDT.

📥 Download Datasheet

Datasheet Details

Part number 9DBL0643
Manufacturer IDT
File Size 321.02 KB
Description 6-output 3.3V LP-HCSL Zero-Delay Buffer
Datasheet download datasheet 9DBL0643 Datasheet

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Other Datasheets by IDT

Part Number Description
9DBL0641 6-output 3.3V PCIe Zero-Delay Buffer
9DBL06 6-output 3.3V PCIe Zero-Delay Buffer
9DBL0651 6-output 3.3V PCIe Zero-Delay Buffer
9DBL0653 6-output 3.3V LP-HCSL Zero-Delay Buffer
9DBL02 2-output 3.3V PCIe Zero-Delay Buffer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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6-output 3.3V LP-HCSL Zero-Delay Buffer with LOS Indicator 9DBL06x3 Datasheet General Description The 9DBL06x3 devices are 3.3V members of IDT's Full-Featured PCIe clock family. They support PCIe Gen1-4 Common Clock (CC) architectures and also support NVLINK applications. The 9DBL06x3 parts have a Loss of Signal (LOS) indicator to support fault-tolerant, high reliability systems. Recommended Application PCIe Gen1-4 and NVLINK clock distribution for Riser Cards, Storage, Networking, JBOD, Communications, Access Points Output Features ▪ Loss Of Signal (LOS) open drain output ▪ 6– 1-200 MHz Low-Power (LP) HCSL DIF pairs ▪ 9DBL0643 default Zout = 100Ω ▪ 9DBL0653 default Zout = 85Ω ▪ Easy AC-coupling to other logic families, see IDT application note AN-891.