FDC654P Datasheet and Specifications PDF

These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially.

-3.6 A, -30 V. RDS(ON) = 0.075 Ω @ VGS = -10 V RDS(ON) = 0.125 Ω @ VGS = -4.5 V. SuperSOTTM-6 package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. SOT.

This P−Channel Logic Level MOSFET is produced using onsemi’s advanced POWERTRENCH process. It has been optimized for battery power management applications. Features • −3.6 A, −30 V. RDS(ON) = 75 mW @ .

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*3.6 A,
*30 V. RDS(ON) = 75 mW @ VGS =
*10 V RDS(ON) = 125 mW @ VGS =
*4.5 V
* Low Gate Charge (6.2 nC typical)
* High Performance Trench Technology for Extremely Low RDS(ON)
* These Device is Pb
*Free and Halogen Free Applications
* Battery Management
* Load Switch
* Battery Protection ABSOLUTE M.