The QL2009 is a 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility.
| Package | LFQFP |
|---|---|
| Operating Voltage | 5 V |
| Max Voltage (typical range) | 5.25 V |
| Min Voltage (typical range) | 4.75 V |
| Max Frequency | 135 MHz |
| Length | 20 mm |
| Width | 20 mm |
| Max Operating Temp | 70 °C |
Unknown Manufacturer
Pin TDI TRSTB TMS TCK TDO STM I/ACLK I/GCLK I I/O VCC GND Function Test Data In for JTAG Active low Reset for JTAG Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG Special Test Mo.
-3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 672 Logic Cells 3-35 QL2009 PRODUCT SUMMARY The Q.
Unknown Manufacturer
Pin TDI TRSTB TMS TCK TDO STM I/ACLK I/GCLK I I/O VCC GND Function Test Data In for JTAG Active low Reset for JTAG Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG Special Test Mo.
-3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 672 Logic Cells 3-35 QL2009 PRODUCT SUMMARY The Q.
Unknown Manufacturer
Pin TDI TRSTB TMS TCK TDO STM I/ACLK I/GCLK I I/O VCC GND Function Test Data In for JTAG Active low Reset for JTAG Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG Special Test Mo.
-3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 672 Logic Cells 3-35 QL2009 PRODUCT SUMMARY The Q.
Unknown Manufacturer
Pin TDI TRSTB TMS TCK TDO STM I/ACLK I/GCLK I I/O VCC GND Function Test Data In for JTAG Active low Reset for JTAG Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG Special Test Mo.
-3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 672 Logic Cells 3-35 QL2009 PRODUCT SUMMARY The Q.
| Seller | Inventory | Price Breaks | Buy |
|---|---|---|---|
| ICPartonline | 6733 | 1+ : 15 USD 10+ : 14.25 USD 100+ : 13.5 USD 1000+ : 12.75 USD |
View Offer |
| Quest | 179 | 1+ : 13.65 USD 38+ : 13.125 USD 77+ : 12.6 USD 160+ : 12.075 USD |
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| Part Number | Manufacturer | Description |
|---|---|---|
| QL2009-1PF144I | Unknown Manufacturer | 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility |
| QL2009-0PQ208C | Unknown Manufacturer | 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility |
| QL2009-2PF144C | Unknown Manufacturer | 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility |
| QL2009-0PF144I | Unknown Manufacturer | 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility |
| QL2009-0PQ208I | Unknown Manufacturer | 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility |
| QL2009-1PB256I | Unknown Manufacturer | 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility |
| QL2009-2PF144I | Unknown Manufacturer | 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility |