| Part Number | SN74LS112A Datasheet |
|---|---|
| Manufacturer | Motorola Semiconductor |
| Overview | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the . individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the trut. |
SN74LS112A Datasheet PDF
The SN74LS112A is a DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP.
| Part Number | SN74LS112A Datasheet |
|---|---|
| Description | Dual J-K Negative-Edge-Triggered Flip-Flops |
| Manufacturer | Texas Instruments |
| Overview | PACKAGE OPTION ADDENDUM 24-Aug-2018 PACKAGING INFORMATION Orderable Device JM38510/07102BEA Status Package Type Package Pins Package (1) Drawing Qty ACTIVE CDIP J 16 1 Eco Plan . A42 POST-PLATE A42 A42 A42 A42 POST-PLATE A42 A42 A42 A42 CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) N / A for Pkg Type Op Temp (°C) -55 to 125 N / A for Pkg Type -55 to 125 N / A for Pkg Type -55 to 125 N / A for Pkg Type -55 to 125 N / A for Pkg Type -55 to 125 N /. |