W196 Datasheet and Specifications PDF

W196 CPU Clock Outputs 0 through 1: These two CPU clocks run at a frequency set by FS0:1 or the serial data interface. See Table 1 and Table 5. Output voltage swing is set by the voltage applied to .

* Maximized EMI suppression using Cypress’s Spread Spectrum Technology
* System frequency synthesizer for 440BX, 440ZX, and VIA Apollo Pro-133
* I2C programmable to 155 MHz (32 selectable frequencies)
* Two skew-controlled copies of CPU output
* Seven copies of PCI output (synchronous w/CPU output) .

CPU Clock Outputs 0 through 1: These two CPU clocks run at a frequency set by FS0:1 or the serial data interface. See Table 1 and Table 5. Output voltage swing is set by the voltage applied to VDDQ2. .

* Maximized EMI suppression using Cypress’s Spread Spectrum Technology
* System frequency synthesizer for 440BX, 440ZX, and VDDQ2 = 2.5V±5% CPU Cycle to Cycle Jitter: .