54AC11 Datasheet | Specifications & PDF Download

54AC11112, 74AC11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS073A – JUNE 1989 – REVISED APRIL 1993 • Flow-Through Archi

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54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configuration Min

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CD54AC112, CD74AC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS325 – JANUARY 2003 D AC Types Feature 1.5-V to 5.5-V Opera

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• Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configuration Minimizes High-Speed Switching Noise • EPIC™ (Enhanced-Perform

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www.DataSheet4U.com 54AC11 Triple 3-Input AND Gate July 1998 54AC11 Triple 3-Input AND Gate General Description The ’AC11 contains three 3-input AN

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ăą • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise • EPIC (Enhanced-Perf

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ăą 54AC11027, 74AC11027 TRIPLE 3ĆINPUT POSITIVEĆNOR GATES • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configurations Mi

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• Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise • EPIC™ (Enhanced-Perform

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ăą 54AC11109, 74AC11109 DUAL JĆK POSITIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH CLEAR AND PRESET SCAS450 − MARCH 1987 − REVISED APRIL 1993 • Flow-Through Ar

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54AC11521, 74AC11521 8-BIT IDENTITY COMPARATORS • Compares Two 8-Bit Words • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND

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54AC11534, 74AC11534 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS037A – JULY 1987 – REVISED APRIL 1993 • Eight D-Type Flip-Flops

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• Applications Include: Buffer/Storage Registers, Shift Registers, Pattern Generators • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VC

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ą • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise • EPIC (Enhanced-Perfo

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ą 54AC11238, 74AC11238 3ĆLINE TO 8ĆLINE DECODERS/DEMULTIPLEXERS ą SCAS039A − APRIL 1988 − REVISED APRIL 1993 • Designed Specifically for High-Speed

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• Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise • EPIC™ (Enhanced-Perform

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D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V SN54AC11 . . . J OR W PACKAGE SN74AC11 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) 1A 1 1

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• 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configu

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54AC11253, 74AC11253 DUAL 1-OF-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS SCAS041A – MAY 1988 – REVISED APRIL 1993 • Permits Multiplexing Fro

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D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V SN54AC11 . . . J OR W PACKAGE SN74AC11 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) 1A 1 1

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D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V SN54AC11 . . . J OR W PACKAGE SN74AC11 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) 1A 1 1

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