74HC27 Datasheet | Specifications & PDF Download

TECHNICAL DATA KK74HC273A Octal D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS The KK74HC273A is identical in pinout to

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CD54HC273, CD74HC273 CD54HCT273, CD74HCT273 SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022 CDx4HC(T)273 High-Speed CMOS Logic Octal D-Type Flip-Flop

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Data sheet acquired from Harris Semiconductor SCHS132C August 1997 - Revised September 2003 CD54HC27, CD74HC27, CD54HCT27, CD74HCT27 High-Speed CMOS

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Triple 3-Input NOR Gate High–Performance Silicon–Gate CMOS The MC54/74HC27 is identical in pinout to the LS27.

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MM74HC273 Octal D-Type Flip-Flops with Clear September 1983 Revised May 2005 MM74HC273 Octal D-Type Flip-Flops with Clear General Description The M

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CD54HC273, CD74HC273 CD54HCT273, CD74HCT273 SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022 CDx4HC(T)273 High-Speed CMOS Logic Octal D-Type Flip-Flop

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal D Flip-Flop with Common Clock and Reset High–Performance Silicon–Gate CMOS The MC54/74HC273A is identica

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M54HC273 M74HC273 OCTAL D TYPE FLIP FLOP WITH CLEAR . . . . . . . . HIGH SPEED fMAX = 67 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (M

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Advance Information MC74HC27A Triple 3-Input NOR Gate High–Performance Silicon–Gate CMOS The MC74HC27A is id

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DATA SHEET www.onsemi.com Octal D Flip-Flop with Common Clock and Reset High−Performance Silicon−Gate CMOS MC74HC273A, MC74HCT273A The MC74HC273A/M

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TECHNICAL DATA KK74HC27A Triple 3-Input NOR Gate The KK74HC27A is high-speed Si-gate CMOS device and are pin compatible with low power Schottky TTL

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M54HC279 M74HC279 QUAD S - R LATCH . . . . . . . . HIGH SPEED tPD = 12 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA (MAX.) AT TA = 25 °C

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HD74HC279 Quad. S–R Latches Description The latch is ideally suited for use as temporary stage for binary information processing and input/output uni

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M74HC27 TRIPLE 3-INPUT NOR GATE s s s s s s s HIGH SPEED: tPD = 9ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA=25°C HIGH N

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HD74HC27 Triple 3-input NOR Gates Features • • • • • High Speed Operation: tpd = 10 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads

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HD74HC273 Octal D-type Flip-Flops (with Clear) Description This device contains 8 master-slave flip-flops with a common clock and common clear. Data

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HD74HC273 Octal D-type Flip-Flops (with Clear) REJ03D0604-0300 Rev.3.00 Mar 25, 2009 Description This device contains 8 master-slave flip-flops with

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HD74HC27 Triple 3-input NOR Gates Features • High Speed Operation: tpd = 10 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • W

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HD74HC279 Octal D-type Flip-Flops (with Clear) REJ03D0605–0200 (Previous ADE-205-483) Rev.2.00 Jan 31, 2006 Description The latch is ideally suited

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74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger Rev. 7 — 6 September 2021 Product data sheet 1. General description The

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