| Part Number | Description | Manufacture |
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Octal Bus Transceivers • Operating voltage range of 4.5 V to 5.5 V • High-Current 3-state outputs drive bus lines directly or up to 15-LSTTL loads • Low power consumption, 80-µA maximum ICC • Typical tpd = 14 ns • ±6-mA output drive at 5 V • Low input current of 1 µA maxim |
 Texas Instruments |
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DUAL J-K FLIP-FLOP |
 National Semiconductor |
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Dual JK flip-flop s Low-power dissipation s Complies with JEDEC standard no. 7A s ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. s Multiple package options s Specified from −40 °C to +80 °C and from −40 °C to +125 °C. Phil |
 Philips |
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Dual 4-channel analog multiplexer/demultiplexer four independent inputs/outputs (nY0, nY1, nY2 and nY3) and a common input/output (nZ). A digital enable input (E) and two digital select inputs (S0 and S1) are common to both switches. When E is HIGH, the switches are turned off. Inputs include clam |
 nexperia |
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QUADRUPLE 2-INPUT NAND GATES • Wide Supply Voltage Range from 4.5V to 5.5V • Pin Compatible with Low Power Schottky (LSTTL) • Inputs Are TTL Voltage Level Compatible • Sinks or sources 4mA at Vcc = 4.5V • CMOS low power consumption • Schmitt Trigger Action at All Inputs • ESD Pr |
 Diodes |
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Octal D-type flip-flop a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-im |
 NXP |
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Dual retriggerable monostable multivibrator and benefits DC triggered from active HIGH or active LOW inputs Retriggerable for very long pulses up to 100 % duty factor Direct reset terminates output pulse Schmitt-trigger action on all inputs except for the reset input ESD protection: |
NXP |
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Dual 2-to-4 line decoder/demultiplexer an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-4 demultiplexer application. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inp |
NXP |
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2-input AND gate • Wide supply voltage range from 2.0 V to 6.0 V • CMOS low power dissipation • High noise immunity • Symmetrical output impedance • Balanced propagation delays • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Input levels: • For |
nexperia |
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Dual D-type flip-flop and benefits • Wide supply voltage range from 2.0 to 6.0 V • CMOS low power dissipation • High noise immunity • Input levels: • For 74HC74: CMOS level • For 74HCT74: TTL level • Symmetrical output impedance • High noise immunity • Balanced propagatio |
nexperia |
| Total 1383 results |
