74S10 Datasheet | Specifications & PDF Download

54S10/74S10 STTL 3 ： tpd=3ns Pd=19mW/ （1/3） ： ： ： B H × L × Y L H H H A H L × × C H × × L 74Ⅱ Vcc VIH VIL IOH IOL TA -40 4.75 2 0.

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DM74S10 Triple 3-Input NAND Gate August 1986 Revised April 2000 DM74S10 Triple 3-Input NAND Gate General Description This device contains three inde

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PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 PACKAGING INFORMATION Orderable Device SN74S1050D Status Package Type Package Pins Package Eco Pla

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D Designed to Reduce Reflection Noise D Repetitive Peak Forward Current to 200 mA D 16-Bit Array Structure Suited for Bus-Oriented Systems D Package O

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SN5410, SN54LS10, SN54S10, SN7410, SN74LS10, SN74S10 TRIPLE 3-INPUT POSITIVE-NAND GATES SDLS035A – DECEMBER 1983 – REVISED APRIL 2003 PRODUCTION DATA

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D Designed to Reduce Reflection Noise D Repetitive Peak Forward Current to 200 mA D 12-Bit Array Structure Suited for Bus-Oriented Systems description

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 Product Introduction Token Offers Dielectric RF Filters for Telecoms. Features :  Suitable for surface mount and reflow soldering.  Excellent mech

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