EPLDs Datasheet | Specifications & PDF Download

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fax id: 61071CY7C342B CY7C342B Features • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array

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E PL D CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDs Features • Erasable, user-configurable CMOS EPLDs capable of implementing high-

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May 1995, ver. 1 Features EP220 & EP224 ® Classic EPLDs Data Sheet s High-performance, low-power Erasable Programmable Logic Devices (EPLDs) with 8 m

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May 1995, ver. 1 Features EP220 & EP224 ® Classic EPLDs Data Sheet s High-performance, low-power Erasable Programmable Logic Devices (EPLDs) with 8 m

(1 views)