The ’AC/’ACT821 consists of ten D-type edge-triggered
flip-flops. The buffered Clock (CP) and buffered Output En-
able (OE) are common to all flip-flops. The flip-flops will store
the state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH CP transition.
With OE LOW the contents of the flip-flops are available at
the outputs. When OE is HIGH the outputs go to the high im-
pedance state. Operation of the OE input does not affect the
state of the flip-flops.
The ’AC/’ACT821 is functionally and pin compatible with the
OE CP D
H = HIGH Voltage Level
L = LOW Voltage Level
Z = HIGH Impedance
N = LOW-to-HIGH Clock Transition
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.