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National Semiconductor Electronic Components Datasheet

54ACT823 Datasheet

9-Bit D Flip-Flop

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54ACT823 pdf
March 1993
54ACT 74ACT823
9-Bit D Flip-Flop
General Description
The ’ACT823 is a 9-bit buffered register It features Clock
Enable and Clear which are ideal for parity bus interfacing in
high performance microprogramming systems The
’ACT823 offers noninverting outputs and is fully compatible
with AMD’s Am29823
www.DataSheet4U.com
Features
Y Outputs source sink 24 mA
Y TRI-STATE outputs for bus interfacing
Y Inputs and outputs are on opposite sides
Y ’ACT823 has TTL-compatible inputs
Logic Symbols
IEEE IEC
Connection Diagrams
Pin Assignment
for DIP Flatpak and SOIC
TL F 9894–1
TL F 9894 – 2
TL F 9894 – 3
Pin Assignment
for LCC
Pin Names
D0 – D8
O0 – O8
OE
CLR
CP
EN
Description
Data Inputs
Data Outputs
Output Enable
Clear
Clock Input
Clock Enable
FACTTM is a trademark of National Semiconductor Corporation
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9894
TL F 9894 – 4
RRD-B30M75 Printed in U S A


National Semiconductor Electronic Components Datasheet

54ACT823 Datasheet

9-Bit D Flip-Flop

No Preview Available !

54ACT823 pdf
Functional Description
The ’ACT823 consists of nine D-type edge-triggered flip-
flops These have TRI-STATE outputs for bus systems or-
ganized with inputs and outputs on opposite sides The buff-
ered clock (CP) and buffered Output Enable (OE) are com-
mon to all flip-flops The flip-flops will store the state of their
individual D inputs that meet the setup and hold time re-
quirements on the LOW-to-HIGH CP transition With OE
LOW the contents of the flip-flops are available at the out-
puts When OE is HIGH the outputs go to the high imped-
ance state Operation of the OE input does not affect
the state of the flip-flops In addition to the Clock and Output
Enable pins there are Clear (CLR) and Clock Enable (EN)
pins These devices are ideal for parity bus interfacing in
high performance systems
When CLR is LOW and OE is LOW the outputs are LOW
When CLR is HIGH data can be entered into the flip-flops
When EN is LOW data on the inputs is transferred to the
outputs on the LOW-to-HIGH clock transition When the EN
is HIGH the outputs do not change state regardless of the
data or clock input transitions
Inputs
OE CLR EN
www.DataSheet4U.comH X L
HXL
HLX
LLX
HHH
L HH
HHL
HHL
LHL
LHL
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Z e High Impedance
L e LOW-to-HIGH Transition
NC e No Change
Function Table
Internal
CP D
Q
LL
LH
XX
XX
XX
XX
LL
LH
LL
LH
L
H
L
L
NC
NC
L
H
L
H
Output
O
Z
Z
Z
L
Z
NC
Z
Z
L
H
Function
High Z
High Z
Clear
Clear
Hold
Hold
Load
Load
Load
Load
Logic Diagram
TL F 9894 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2


Part Number 54ACT823
Description 9-Bit D Flip-Flop
Maker National Semiconductor
Total Page 8 Pages
PDF Download
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