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DF121 - CMOS Gate Array

General Description

DF12x is a family of static, master-slave D flip-flops.

SET and RESET are asynchronous and active low.

Outputs are buffered and change state on the rising edge of the clock.

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Datasheet Details

Part number DF121
Manufacturer AMI
File Size 48.17 KB
Description CMOS Gate Array
Datasheet download datasheet DF121 Datasheet

Full PDF Text Transcription for DF121 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for DF121. For precise diagrams, and layout, please refer to the original PDF.

')[ ® $0,+*  PLFURQ &026 *DWH $UUD Description DF12x is a family of static, master-slave D flip-flops. SET and RESET are asynchronous and active low. Outputs are bu...

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p-flops. SET and RESET are asynchronous and active low. Outputs are buffered and change state on the rising edge of the clock. Logic Symbol DF12x DSQ C RQ Truth Table SN RN LL LH HL HH HH HH IL = Illegal D X X X L H X C Q QN X IL IL XHL XLH ↑LH ↑HL L NC NC NC = No Change Core Logic HDL Syntax Verilog .................... DF12x inst_name (Q, QN, C, D, RN, SN); VHDL...................... inst_name: DF12x port map (Q, QN, C, D, RN, SN); Pin Loading Pin Name D C SN RN DF121 1.0 1.0 2.1 2.2 Equivalent Loads DF122 DF124 1.0 1.0 1.0 1.0 2.1 2.1 2.2 1.0 DF126 1.0 1.0 2.1 1.

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