DESCRIPTION
SET and RESET are asynchronous and active low. Outputs are buffered and change state on the rising edge of the clock. Logic Symbol DF12x DSQ C RQ Truth Table SN RN LL LH HL HH HH HH IL = Illegal D X X X L H X C Q QN X IL IL XHL XLH ↑LH ↑HL L NC NC NC = No Change Core Logic HDL Syntax Verilog .................... DF12x inst_name (Q, QN, C, D, RN, SN); VHDL...................... inst_name: DF12x port map (Q, QN, C, D, RN, SN); Pin Loading Pin Name D C SN RN DF121 1.0 1.0 2.1 2.2 Equivalent Loads DF122 DF124 1.0 1.0 1.0 1.0 2.1 2.1 2.2 1.0 DF126 1.0 1.0 2.1 1.0 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) DF121 10.0 TBD 22.2 DF122 11.0 TBD 25.6 DF124 14.0 TBD 36.1 DF126 16.0 TBD 43.0 a. See page 2-15 for power equation. 3-63 Core Logic ') [ ® $0, +* P
AMI
