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DF422 - CMOS Gate Array

Download the DF422 datasheet PDF. This datasheet also covers the DF421 variant, as both devices belong to the same cmos gate array family and are provided as variant models within a single manufacturer datasheet.

General Description

DF42x is a family of static, master-slave, multiplexed scan D flip-flops.

SET and RESET are asynchronous and active low.

Outputs are buffered and change state on the rising edge of the clock.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DF421-AMI.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number DF422
Manufacturer AMI
File Size 49.59 KB
Description CMOS Gate Array
Datasheet download datasheet DF422 Datasheet

Full PDF Text Transcription for DF422 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for DF422. For precise diagrams, and layout, please refer to the original PDF.

')[ ® $0,+*  PLFURQ &026 *DWH $UUD Description DF42x is a family of static, master-slave, multiplexed scan D flip-flops. SET and RESET are asynchronous and active l...

View more extracted text
iplexed scan D flip-flops. SET and RESET are asynchronous and active low. Outputs are buffered and change state on the rising edge of the clock. Logic Symbol DF42x DS C SD SE R Q Q Truth Table C D RN SD SE SN Q QN ↑HHX LHHL ↑ L HX L H L H ↑ XHHHHH L ↑ XH L HH L H XX L XXH L H XXHXX L H L X X L X X L IL IL L X H X X H NC NC NC = No Change IL = Illegal Condition Core Logic HDL Syntax Verilog .................... DF421x inst_name (Q, QN, C, D, RN, SD, SE, SN); VHDL...................... inst_name: DF421x port map (Q, QN, C, D, RN, SD, SE, SN); Pin Loading Pin Name C D RN SD SE SN DF421 1.0 1.0 2.1 1.0 2.1 2.1 Equivalent Loads

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