IDCS3 - CMOS Gate Array

AMI

General Description

IDCS3 is a non-inverting, CMOS-level Schmitt trigger input buffer piece with voltage hysteresis.

IDCS3 cmos gate array by AMI - Datasheet Preview

Datasheet Details

Part number	IDCS3
Manufacturer	AMI
File Size	17.52 KB
Description	CMOS Gate Array
Datasheet	IDCS3 Datasheet

Full PDF Text Transcription for IDCS3 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for IDCS3. For precise diagrams, and layout, please refer to the original PDF.

,'&6 ® $0,+* PLFURQ &026 *DWH $UUD Description IDCS3 is a non-inverting, CMOS-level Schmitt trigger input buffer piece with voltage hysteresis. Logic Symbol Truth T...

View more extracted text

igger input buffer piece with voltage hysteresis. Logic Symbol Truth Table Pin Loading IDCS3 QC P PADM D PADM QC LL HH Load PADM 4.90 pF HDL Syntax Verilog .................... IDCS3 inst_name (QC, PADM); VHDL...................... inst_name: IDCS3 port map (QC, PADM); Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation. Value TBD 17.0 Units nA Eq-load Propagation Delays Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Delay (ns) From To Parameter 1 PADM QC tPLH tPHL 1.37 1.01 Delay will vary with input conditions. See page 2-17 for interconnect estimates. Number of Equivalent Lo

More Datasheets from AMI

Part Number	Description
IDCI3	CMOS Gate Array
IDCR0	CMOS Gate Array
IDCX3	CMOS Gate Array
IDCX6	CMOS Gate Array