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Description IDCXx is a family of non-inverting, CMOS-level input buffer pieces.
Logic Symbol
Truth Table
IDCXx
QC P PADM D
PADM QC LL HH
HDL Syntax Verilog .................... IDCXx inst_name (QC, PADM); VHDL...................... inst_name: IDCXx port map (QC, PADM);
Pin Loading Pin Name PADM (pF)
Load
IDCX3
IDCX6
4.90 4.90
Power Characteristics
Cell
Equivalent Gates
IDCX3 IDCX6
0.0 0.0
a. See page 2-15 for power equation.
Power Characteristicsa
Static IDD (TJ = 85°C) (nA) TBD
EQLpd (Eq-load) 10.4
TBD
18.1
Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Number of Equivalent Loads
1
IDCX3
From: PADM To: QC
tPLH tPHL
0.63 0.
IDCX3 Datasheet
