IDCS3 Description
IDCS3 is a non-inverting, CMOS-level Schmitt trigger input buffer piece with voltage hysteresis. Logic Symbol Truth Table Pin Loading IDCS3 QC P PADM D PADM QC LL HH Load PADM 4.90 pF HDL Syntax Verilog .................... IDCS3 inst_name (QC, PADM);.