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MG29C10 Datasheet Preview

MG29C10 Datasheet

12-bit microprogram controller

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Features
• A high-performance, low-power CMOS megacell
featuring functional compatibility with the industry
standard 2901
• 4-Bit cascadable bit-slice
• Eight function ALU including addition, two subtraction
and five logic operations on two operands
• Microprogrammable with three groups of three bits each
for ALU function, destination control and source
operand
• Two address architecture provides independent access
to two working registers
• Five source ports for data selection
• Four status flags including carry, zero, overflow and sign
• Equivalent gates:
Standard Cell - 810; Gate Array - 1000
LOGIC SYMBOL
MG29C01
I(8:0)
Q0I
Q3I
RAM0I
RAM3I
CIN
CLK
Q0O
Q3O
F0
F3
GN
PN
COUT
OVR
RAM0O
RAM3O
OE0N
OE3N
Description
MG29C10 is a high-performance 12-bit microprogram
controller. It functions as an address sequencer for con-
trolling the execution of microinstructions in
microprogram memory.
It also controls conditional branching to any microinstruc-
tion within its 4096 word range. There are nine levels of
subroutine nesting with return linkage and looping capa-
bility provided by a last-in, first-out stack.
The MG29C10 has four sources for providing the 12-bit
address during each microinstruction. These four sources
are as follows:
1. A direct external input.
2. A register/counter (R) which retains data loaded dur-
ing an earlier microinstruction.
3. The last-in, first-out stack/file (F).
4. The address counter/register which usually incre-
ments the addresses.
The MG29C10 consists of six functional blocks: an
instruction PLA, a multiplexer, a register/counter, a zero
detector, a 9-word by 12-bit stack, a microprogram
counter register, and an incrementer.
D(3:0)
A(3:0)
B(3:0)
Y(3:0)
5-7




AMI

MG29C10 Datasheet Preview

MG29C10 Datasheet

12-bit microprogram controller

No Preview Available !

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%LW 0LFURSURJUDP &RQWUROOHU
®
'LJLWDO 6RIW 0HJDFHOOV
Pin Description
SIGNAL
CCN
CCENN
CI
RLDN
CLK
D(11:0)
I(3:0)
FULLN
PLN
MAPN
VECTN
Y(11:0)
TYPE
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
SIGNAL DESCRIPTIONS
Used as test input criterion. Active low.
Enables CCN. Active low.
Carry input to the low order of the microprogram counter.
Forces loading of register/counter regardless of instruction or condition. Active low.
Master input clock.
Direct data input to register/counter and multiplexer. D(0) is the LSB.
Instruction inputs. I(0) is the LSB.
Goes low when the internal stack is full. Active low.
Used to select #1 source (usually a pipeline register) as the direct input source.
Used to select #2 source (usually a mapping ROM or PLA) as the direct input source.
Used to select #3 source (usually an interrupt starting address) as the direct input source.
Address to microprogram memory. Y(0) is the LSB.
5-8


Part Number MG29C10
Description 12-bit microprogram controller
Maker AMI
Total Page 2 Pages
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