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ODCHXX24 Datasheet Preview

ODCHXX24 Datasheet

CMOS Gate Array

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Description
ODCHXX24 is a high performance, 24 mA, non-inverting, TTL-level output buffer piece.
Logic Symbol
Truth Table
Pin Loading
ODCHXX24
A
A PADM
LL
HH
Load
A 14.5 eql
PADM
HDL Syntax
Verilog .................... ODCHXX24 inst_name (PADM, A);
VHDL...................... inst_name: ODCHXX24 port map (PADM, A);
Power Characteristics
Parameter
Static IDD (TJ = 85°C)
EQLpd
See page 2-15 for power equation.
Value
TBD
249.7
Units
nA
Eq-load
Output Propagation Delays
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Delay (ns)
From
To Parameter
15
A
PADM
tPLH
tPHL
0.67
0.70
Delay will vary with input conditions. See page 2-17 for interconnect estimates.
50
1.13
1.05
Capacitive Load (pF)
100
1.78
1.49
200
3.10
2.35
300 (max)
4.42
3.22
4-14


Part Number ODCHXX24
Description CMOS Gate Array
Maker AMI
Total Page 1 Pages
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