A67P0618 Datasheet | AMIC Technology

.. A67P0618/A67P9336 Series Preliminary Document Title 2M X 18, 512K X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History Rev. No. 1M X 18, 512K X 36 LVTTL, Pipelined ZeBLTM SRAM History Initial issue Issue Date September, 20, 2004 Remark Preliminary PRELIMINARY (September, 2004, Version 0.0) AMIC Technology, Corp. A67P0618/A67P9336 Series Preliminary Features Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +2.5V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled and...