AMIS-720649: Contact Image Sensor
Data Sheet
3.0 Key Features
• 600dpi
• 344 image sensor elements (pixels)
• 42.3µm pixel center-to-center spacing (23.62dots/mm)
• On-chip amplifier
• Single 5.0V power supply
• 5.0V input clocks
• 2.5MHz maximum pixel rate
• Parallel / integrate and transfer
• Power-down circuit
• High sensitivity
• Low power
• Low noise
4.0 Unique Features
There are five unique features incorporated in the AMIS-720649 which improve the sensor’s performance.
4.1 Pixel-to-Pixel Offset Cancellation Circuit
The sensor employs a pixel-to-pixel offset cancellation circuit, which reduces the fix pattern noise (FPN), and amplifier offsets. In
addition, this innovative circuit design greatly improves the optical linearity and low noise sensitivity.
4.2 Parallel Integrate, Transfer and Hold
The sensor has a parallel integrate, transfer and hold feature, which allows the sensor to be read out while photon integration is taking
place. These features are approached through the use of an integrate and hold cell, located at each pixel site. Each pixel’s charge is
wwrewa.DdaftraoSmheitest4sUto.croamge site as the sensor’s shift register sequentially transfers each pixel’s charge onto a common video line.
4.3 Dual Scan Initiation Inputs, GBST and SI
Each sensor has two scan initiation inputs, the global start pulse (GBST) and the start pulse (SI). These clocks help to reduce the
sensor-to-sensor transition fix pattern noise by initializing and preprocessing all sensors simultaneously before they start their readout
scan. The internal shift register starts the scan after GBST is clocked in on the falling edge of the clock input (CLK).
The start input control (SIC) selects the first sensor in a sequence of cascaded sensors to operate with 29 clock cycles of delay by
connecting it to Vdd on the first sensor, and to ground for all subsequent sensors. Then, only the first sensor clocks out 29 inactive
pixels before accessing its first active pixel. During these 29 clock cycles, the first sensor and all of the subsequent cascaded sensors
cycle through their pre-scan initialization process. After initialization, only the first sensor starts its read cycle with its first-active pixel
appearing on the 30th clock cycle. The second and subsequent sensors await the entry of their SI. Furthermore, the first sensor’s SI is
left unconnected, while the subsequent sensors all have their SI’s connected to the end-of-scan (SO) of their respective preceding
sensor. The external scan SI is connected to all of the sensors' GBST inputs.
As the first sensor completes its scan, its SO, appears one pixel before its last pixel. The second and subsequent sensors will then start
their registers one clock cycle before the appearance of their respective first pixels, and their SO also appears one pixel before their last
pixel.
AMI Semiconductor – Dec. 05, M-20488-001
www.amis.com
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