AT89LP52
Key Features
- Enhanced 8051 Architecture
- Single Clock Cycle per Byte Fetch - 12 Clock per Machine Cycle patibility Mode
- Dual Data Pointers - 4-level Interrupt Priority
- Peripheral Features - Three 16-bit Timer/Counters with Clock Out Modes - Enhanced UART
- Automatic Address Recognition
- Framing Error Detection
- SPI and TWI Emulation Modes
- Programmable Watchdog Timer with Software Reset and Prescaler
- Special Microcontroller Features
- I/O and Packages - Up to 36 Programmable I/O Lines - Green (Pb/Halide-free) Packages
