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AT76C713 - USB BRIDGE CONTROLLER

Description

Table 5-1.

Name JTAG Signals TCK TDI TDO TMS Port Signals Port A is used in configurations with external memory, where it acts as the AD0-7 address and/or data bus.

Features

  • Advanced RISC Architecture, 130 Powerful Instructions, Most Single-Clock Cycle Execution.
  • Clock Generator Provides CPU Rates up to 48 MHz.
  • Only One External Clock Crystal of 12 MHz Can Generate All the Required System Clocks:.
  • Internal Clock for Standard UART Rates.
  • A 48 MHz and 96 MHz Clock for USB Data Recovery.
  • AVR Processor and System Clock.
  • Full-speed USB Interface (12 Mbits per Second) 2.0 Compliant.
  • JTAG (IEEE std.

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Features • Advanced RISC Architecture, 130 Powerful Instructions, Most Single-Clock Cycle Execution • Clock Generator Provides CPU Rates up to 48 MHz • Only One External Clock Crystal of 12 MHz Can Generate All the Required System Clocks: – Internal Clock for Standard UART Rates – A 48 MHz and 96 MHz Clock for USB Data Recovery – AVR Processor and System Clock • Full-speed USB Interface (12 Mbits per Second) 2.0 Compliant • JTAG (IEEE std. 1149.
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