Datasheet Summary
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Features
General
- High-performance, Low-power secureAVR RISC Architecture
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- 133 Powerful Instructions (Most Executed in a Single Clock Cycle)
- Linear Addressing of up to 8M Bytes of Code and up to 16M Bytes of Data Low-power Idle and Power-down Modes Bond Pad Locations Conforming to ISO 7816-2 ESD Protection to ± 6000V Operating Ranges: from 2.7V to 5.5V pliant with GSM, 3GPP and EMV 2000 Specifications; PC Industry patible Available in Wafers, Modules and Industry-standard Packages
Memory
- 192K Bytes of ROM Program Memory
- 72K Bytes of EEPROM, Including 128-byte OTP Area and 384-byte Bit-addressable Area
- 1 to 128-byte Program/Erase
- 1 ms...