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Actel Corporation
Actel Corporation

A3P1000 Datasheet Preview

A3P1000 Datasheet

(A3Pxxx) ProASIC3 Flash Family FPGAs

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A3P1000 pdf
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ProASIC3 Flash Family FPGAs
Advanced v0.2
Features and Benefits
High Capacity
• 30 k to 1 Million System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 288 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
• Live-At-Power-Up Level 0 Support
• Single-Chip Solution
• Retains Programmed Design When Powered Off
On-Chip User Nonvolatile Memory
• 1 kbit of FlashROM (FROM)
Performance
• 150+ MHz Internal System Performance with 3.3 V,
66 MHz 64-bit PCI (except A3P030)
• Up to 350 MHz External System Performance
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit AES Decryption via
JTAG (IEEE1532-compliant) (except A3P030)
• FlashLock™ to Secure FPGA Contents
Low Power
• 1.5 V Core Voltage for Low Power
• Support for 1.5-V-Only Systems
• Low-Impedance Flash Switches
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• Ultra-Fast Local and Long-Line Network
• Enhanced High-Speed, Very Long-Line Network
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages – Up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X (except
A3P030), and LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL and LVDS (A3P250
and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable I/Os (A3P030 only)
• Programmable Output Slew Rate and Drive Strength
• Weak Pull-Up/Down
• IEEE1149.1 (JTAG) Boundary-Scan Test
• Pin-Compatible Packages Across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL
(except A3P030)
• Six CCC Blocks Total, One with an Integrated PLL
• Flexible Phase Shift, Multiply/Divide, and Delay
Capabilities
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
SRAMs and FIFOs (except A3P030)
• Variable-Aspect Ratio 4,608-bit RAM Blocks (x1, x2, x4,
x9, x18 Organizations Available)
• True Dual-Port SRAM (except x18)
• 24 SRAM and FIFO Configurations with Synchronous
Operation up to 350 MHz
• Programmable Embedded FIFO Control Logic
Table 1 • ProASIC3 Product Family
System Gates
VersaTiles (D-Flip-Flops)
RAM kbits (1,024 bits)
4,608 Bit Blocks
FlashROM (FROM) Bits
Secure (AES) ISP
Integrated PLL in CCCs
VersaNet Globals1
I/O Banks
Maximum User I/Os
Package Pins
QFN
VQFP
TQFP
PQFP
FBGA
A3P030
30 k
768
1k
6
2
81
QN132
VQ100
A3P060
60 k
1,536
18
4
1k
Yes
1
18
2
96
VQ100
TQ144
FG144
A3P125
125 k
3,072
36
8
1k
Yes
1
18
2
133
A3P250
250 k
6,144
36
8
1k
Yes
1
18
4
157
A3P400
400 k
9,216
54
12
1k
Yes
1
18
4
194
A3P600
600 k
13,824
108
24
1k
Yes
1
18
4
227
A3P1000
1M
24,576
144
32
1k
Yes
1
18
4
288
VQ100
TQ144
PQ208
FG144
VQ100
PQ208
PQ208
PQ208
PQ208
FG144, FG256 FG144, FG256, FG144, FG256, FG144,
FG484
FG484
FG256, FG484
Notes:
1. Six chip (main) and three quadrant global networks are available for A3P060 and above.
2. For higher densities and support of additional features, refer to the ProASIC3E Flash FPGAs datasheet.
January 2005
© 2005 Actel Corporation
i
See Actel’s website for the latest version of the datasheet.



Actel Corporation
Actel Corporation

A3P1000 Datasheet Preview

A3P1000 Datasheet

(A3Pxxx) ProASIC3 Flash Family FPGAs

No Preview Available !

A3P1000 pdf
www.DataSheet4U.com
ProASIC3 Flash Family FPGAs
I/Os Per Package
A3P030 A3P060 A3P125
A3P250
A3P400
A3P600
A3P1000
Package
QN132
VQ100
TQ144
PQ208
FG144
FG256
FG484
81
79
– – –– – –
71 71 68 13 –
91 100 –
133 151
34
151
33
96 97 97 24 97 24
– – 157 38 178 38
– – – – 194 38
Notes:
1. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
2. FG256 and FG484 are footprint-compatible packages.
3. Advanced information subject to change.
154
97
179
227
35
24
45
56
154
97
179
288
Ordering Information
35
24
45
68
A3P1000 _ 1
FG 144
I
Application (Ambient Temperature Range)
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
PP = Pre-Production
ES = Engineering Silicon (Room Temperature Only)
Package Lead Count
Package Type
QN = Quad Flat No Leads (0.5 mm pitch)
Speed Grade
VQ = Very Thin Quad Flat Pack (0.5 mm pitch)
TQ = Thin Quad Flat Pack (0.5 mm pitch)
PQ = Plastic Quad Flat Pack (0.5 mm pitch)
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
Part Number
F = 20% Slower than Standard*
Blank = Standard
1 = 15% Faster than Standard
2 = 25% Faster than Standard
A3P030 = 30,000 System Gates
A3P060 = 60,000 System Gates
A3P125 = 125,000 System Gates
A3P250 = 250,000 System Gates
A3P400 = 400,000 System Gates
A3P600 = 600,000 System Gates
A3P1000 = 1,000,000 System Gates
Note: *DC and switching characteristics for –F speed grade targets based only on simulation.
The characteristics provided for –F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be
added and will be reflected in future revisions of this document. The –F speed grade is only supported in commercial temperature
range.
Figure 1 • Ordering Information
ii Advanced v0.2


Part Number A3P1000
Description (A3Pxxx) ProASIC3 Flash Family FPGAs
Maker Actel Corporation
Total Page 30 Pages
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