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Advanced Micro Devices

PALCE20V8 Datasheet Preview

PALCE20V8 Datasheet

EE CMOS 24-Pin Universal Programmable Array Logic

No Preview Available !

FINAL
COM’L: H-5/7/10/15/25, Q-10/15/25
IND: H-15/25, Q-20/25
PALCE20V8 Family
EE CMOS 24-Pin Universal Programmable Array Logic
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
s Pin and function compatible with all GAL
20V8/As
s Electrically erasable CMOS technology pro-
vides reconfigurable logic and full testability
s High-speed CMOS technology
— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
s Direct plug-in replacement for a wide range of
24-pin PAL devices
s Programmable enable/disable control
s Outputs individually programmable as
registered or combinatorial
GENERAL DESCRIPTION
The PALCE20V8 is an advanced PAL device built with
low-power, high-speed, electrically-erasable CMOS
technology. Its macrocells provide a universal device
architecture. The PALCE20V8 is fully compatible with
the GAL20V8 and can directly replace PAL20R8 series
devices and most 24-pin combinatorial PAL devices.
Device logic is automatically configured according to the
user’s design specification. A design is implemented
using any of a number of popular design software pack-
ages, allowing automatic creation of a programming file
based on Boolean or state equations. Design software
also verifies the design and can provide test vectors for
the finished device. Programming can be accomplished
on standard PAL device programmers.
The PALCE20V8 utilizes the familiar sum-of-products
(AND/OR) architecture that allows users to implement
BLOCK DIAGRAM
s Peripheral Component Interconnect (PCI)
compliant
s Preloadable output registers for testability
s Automatic register reset on power-up
s Cost-effective 24-pin plastic SKINNYDIP and
28-pin PLCC packages
s Extensive third-party software and programmer
support through FusionPLD partners
s Fully tested for 100% programming and func-
tional yields and high reliability
s Programmable output polarity
s 5-ns version utilizes a split leadframe for
improved performance
complex logic functions easily and efficiently. Multiple
levels of combinatorial logic can always be reduced to
sum-of-products form, taking advantage of the very
wide input gates available in PAL devices. The equa-
tions are programmed into the device through floating-
gate cells in the AND logic array that can be erased
electrically.
The fixed OR array allows up to eight data product terms
per output for logic functions. The sum of these products
feeds the output macrocell. Each macrocell can be
programmed as registered or combinatorial with an
active-high or active-low output. The output configura-
tion is determined by two global bits and one local bit
controlling four multiplexers in each macrocell.
I1 – I10
10
CLK/I0
Programmable AND Array
40 x 64
Input
Mux.
MACRO
MC0
MACRO
MC1
MACRO
MC2
MACRO
MC3
MACRO
MC4
MACRO
MC5
MACRO
MC6
MACRO
MC7
Input
Mux.
OE/I11 I12 I/O0 I/O1 I/O2 I/O4 I/O4 I/O5 I/O6 I/O7 I13
Publication# 16491 Rev. D Amendment /0
Issue Date: February 1996
16491D-1
2-155




Advanced Micro Devices

PALCE20V8 Datasheet Preview

PALCE20V8 Datasheet

EE CMOS 24-Pin Universal Programmable Array Logic

No Preview Available !

AMD
CONNECTION DIAGRAMS
(Top View)
SKINNYDIP
CLK/I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 I13
22 I/O7
21 I/O6
20 I/O5
19 I/O4
18 I/O3
17 I/O2
16 I/O1
15 I/O0
14 I12
13 OE/I11
16491D-2
Note:
Pin 1 is marked for orientation.
PIN DESIGNATIONS
CLK = Clock
GND = Ground
I = Input
I/O = Input/Output
NC = No Connect
OE = Output Enable
VCC = Supply Voltage
PLCC/LCC
4 3 2 1 28 27 26
I3 5
I4 6
I5 7
NC 8
25 I/O6
24 I/O5
23 I/O4
22 NC
I6 9
21 I/O3
I7 10
20 I/O2
I8 11
19 I/O1
12 13 14 15 16 17 18
16491D-3
2-156
PALCE20V8 Family


Part Number PALCE20V8
Description EE CMOS 24-Pin Universal Programmable Array Logic
Maker Advanced Micro Devices
Total Page 16 Pages
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