UT8SP2M48 Overview
Chip Enable 0, Input, Active LOW: Sampled on the rising edge of CLK. Used in conjunction with CS1 and CS2 to select or deselect the device.
UT8SP2M48 Key Features
- Clk to Q = 7ns Clock Enable (CEN) pin to enable clock and suspend
- Total Dose: 100 krad(Si)
- SEL Immune: ≤ 100MeV-cm2/mg
- SEU error rate: 1.7x10-6 errors/bit-day Package options
- 288-lead CLGA, CCGA, and CBGA Standard Microelectronics Drawing (SMD) 5962-15213
- QMLQ and Q+ pending