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UT8SF2M32 - 64Megabit Flow-thru SSRAM

Datasheet Summary

Description

Chip Enable 0, Input, Active LOW: Sampled on the rising edge of CLK.

Used in conjunction with CS1 and CS2 to select or deselect the device.

Chip Enable 1 Input, Active HIGH: Sampled on the rising edge of CLK.

Features

  •  Synchronous SRAM organized as 2Meg words x 32bit  Continuous Data Transfer (CDT) architecture eliminates wait states between read and write operations  Supports 40MHz to 80MHz bus operations  Internally self-timed output buffer control eliminates the need for synchronous output enable  Registered inputs for flow-thru operations  Single 2.5V to 3.3V supply  Clock-to-output times - Clk to Q = 12ns  Clock Enable (CEN) pin to enable clock and suspend operation  Synchronous self-timed write.

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Datasheet preview – UT8SF2M32

Datasheet Details

Part number UT8SF2M32
Manufacturer Aeroflex Circuit Technology
File Size 351.05 KB
Description 64Megabit Flow-thru SSRAM
Datasheet download datasheet UT8SF2M32 Datasheet
Additional preview pages of the UT8SF2M32 datasheet.

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Full PDF Text Transcription

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Standard Products UT8SF2M32 64Megabit Flow-thru SSRAM Preliminary Datasheet www.aeroflex.com/memories April 2015 FEATURES  Synchronous SRAM organized as 2Meg words x 32bit  Continuous Data Transfer (CDT) architecture eliminates wait states between read and write operations  Supports 40MHz to 80MHz bus operations  Internally self-timed output buffer control eliminates the need for synchronous output enable  Registered inputs for flow-thru operations  Single 2.5V to 3.
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