Description
Symbol CLK
Type Input
CKE
Input
A11 A0-A10
Input Input
CS# Input
RAS#
Input
CAS#
Input
WE#
Input
LDQM, UDQM
Input
AS4C1M16S-C&I
Table 3. Pin Details
Description
Clock: CLK is driven by the system clock.All SDRAM input signals are sampled on the positive edge of CLK.CLK also increments the internal burst counter and controls the output registers.Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.If CKE goes low synchronously with clock (set-up and hold ti
Features
- Fast access time: 5.4/5.4ns.
- Fast clock rate: 166/143 MHz.
- Self refresh mode: standard.
- Internal pipelined architecture.
- 512K word x 16-bit x 2-bank.
- Programmable Mode registers
- CAS Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential or Interleaved
- Burst stop function.
- Individual byte controlled by LDQM and UDQM.
- Auto Refresh and Self Refresh.
- 4096 refresh cycles/64ms.
- CKE power down mode.
- Industrial Tempe.