AS4C256M16D3LB-12BAN dram equivalent, 4gb dram.
- Double-data-rate architecture; two data transfers per clock cycle
- The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
- Bi-directio.
Pin
CK, CK CKE
CS ODT
RAS, CAS, WE DM
(DMU), (DML)
Type
Input Input
Input Input
Input Input
Function
Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and .
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Related datasheet
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